1. Technical Field
The present subject matter relates to semiconductor memories, and more specifically, to three-dimensional NAND flash memory arrays.
2. Background Art
Many types of semiconductor memory are known in the art. Some memory is volatile and will lose its contents if power is removed. Some memory is non-volatile and will hold the information stored in the memory even after power has been removed. One type of non-volatile memory is flash memory which stores charge in a charge storage region of a memory cell. In a floating gate flash cell, a conductive floating gate, positioned between the control gate and the channel of a metal-oxide silicon field effect transistor (MOSFET), is used to store a charge. In a charge trap flash (CTF) cell, a layer of non-conductive material, such as a nitride film, is used to store charge between the control gate and the channel of a MOSFET. The voltage threshold of the MOSFET-based flash cell can be changed by changing the amount of charge stored in the charge storage region of the cell, and the voltage threshold can be used to indicate a value that is stored in the flash cell.
One architecture in common use for flash memories is a NAND flash architecture. In a NAND flash architecture, two or more flash cells are coupled together, source to drain, into a string, with the individual cell control gates coupled to control lines, such as word lines. Select gates, which may be standard MOSFETs, may be coupled to the NAND string at either end, to couple the NAND string to a source line at one end of the NAND string, and to a bit line at the other end of the NAND string.
Some NAND flash devices may create stacks of flash memory cells in a three-dimensional array NAND strings. A stack of flash cells may include any number of flash cells with the source, channel, and drain arranged vertically so that as the cells are positioned, one on top of the other, they form a vertical NAND string. The vertical NAND string may be positioned on top of a select gate that may couple the string to a source line and may have another select gate positioned on top of the vertical NAND string to couple the string to a bit line.